The present invention generally relates to a high quality semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which a latch up condition is avoided.
In the conventional semiconductor integrated circuit, one resistor is provided within one island to increase the degree of integration without taking the electric potential of the island. A description of the conventional circuit will be effected hereinafter with reference to pattern chart of FIG. 5a, an equivalent circuit diagram of FIG. 5b and a sectional view of FIG. 5c. Reference numeral 21 is an n-type island area, reference numeral 22 is a p-type resistance area within the n-type island area 21, and reference numerals 23 and 24 are electrodes taken out from the p-type resistance area 22, with reference numeral 23 being provided at the side of a higher electric potential. Reference numeral 25 is an n-type island area, reference numeral 26 is a p-type separating area for separating the n-type island are 21 from the n-type island area 25, and reference numerals 27 and 28 are electrodes taken out from the n-type island area 25. The electrode 28 is connected with a ground electrode 30 through a p-type resistor 29. When one p-type resistance area 22 is placed within one n-type island area 21, current does not flow between the n-type island area 21 and the p-type resistance area 22 even if the n-type island area 21 is kept floating. Therefore, it is not necessary to obtain the potential of the island area 21. The integration degree is increased with respect to the following two points: (1) a connection area connecting the n-type island area 21 with an electrode is unnecessary, and (2) a connection pattern between a high potential (power supply voltage) and the n-type island area 21 is unnecessary.
In such a case as shown in FIG. 5a, namely, when the n-type island area 25 is relatively close to the n-type island area 21 with the other p-type resistor 29 connected with the n-type island area 25 being grounded, a parasitic PNP transistor 31 is formed in which the p-type resistance area 22, the n-type island area 21 and the p-type separation area 26 respectively constitute an emitter, a base and a collector, and a parasitic NPN transistor 32 is formed in which the n-type island area 21, the p-type separation area 26 and the n-type island area 25 respectively constitute a collector, a base and an emitter. The parasitic transistors 31 and 32 together form a PNPN type thyristor. Since the p-type separation area 26 is spaced away from the ground, an additional resistor 33 is provided between the p-type separation area 26 and ground. The resultant equivalent circuit is shown in FIGS. 5b and 5c. When the p-type separation area 26 is spaced away from the ground, the potential thereof becomes higher so as to turn on the parasitic NPN transistor 32. When the parasitic NPN transistor 32 is turned on, a collector current of the parasitic PNP transistor 31 flows which is a base current of the parasitic PNP transistor 31. The parasitic PNP transistor 31 turns on and a collector current of the parasitic PNP transistor 31 flows which is a h.sub.FE magnification of the base current. The base potential of the parasitic NPN transistor 32 is then further increased by the resistor 33 and more currents are caused to flow. As a result, the currents increase until the parasitic PNP transistor 31 and the parasitic NPN transistor 32 are saturated. Particularly when the resistor 33 is small, or does not exist, excessive currents flow. This latch up condition is especially likely to occur in the case of the PNPN.